The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the production and performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of—and attention to—maximum utilization and yield of wafer real estate.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Modern semiconductor fabrication processes involve numerous processing steps, during which numerous material layers are deposited on a substrate (or wafer). Multiple levels of metal and dielectric are commonly deposited in such processes and, often, new materials or compositions are introduced. The deposition of multiple layers requires repetitive processing steps—and repetitive stresses—to the material layers disposed upon the wafer. The differing physical properties (e.g., coefficient of thermal expansion) of the varied material layers, when subjected to the repetitive stresses of the fabrication process, can cause a number of physical aberrations in the wafer structure.
Even the most minor physical aberrations in the structural integrity of one portion of a wafer can cause significant, and even catastrophic, damage to the entire wafer. Consider, for example, the problems associated with wafer edge aberrations. Often, such aberrations take the form of peeling or blistering of structures along the outer edge of the wafer. On a given wafer (or substrate), active device area may be fabricated to consume nearly the entire surface area of one side of the wafer. Buffer area or margin between the perimeter of the active area and the outer edge of the wafer may be nominal or nearly non-existent. Peeling or blistering of edge structures can directly damage the structure of devices fabricated near the outer perimeter of the wafer. More commonly, however, peeling and blistering of edge structures results in a chaff of small, broken pieces of material and debris that can scatter across the wafer surface and throughout the downstream processes. The propagation of this debris can cause direct damage (e.g., tears and pits) to device structures throughout the wafer. The propagation of this debris can further cause indirect damage to device structures by blocking later etch and deposition processes.
Regardless of the mode of damage done, such edge aberrations have, in the past, usually resulted in a significant yield loss, as wafers exhibiting such aberrations were scrapped completely. It appears that there have previously been no successful systems for remediating such aberrations. Once such aberrations were apparent, a wafer would be scrapped completely so as to prevent debris from contaminating the process flow for later wafers. Where each wafer contained hundreds, if not thousands, of individual devices, a significant and costly yield loss resulted.
As a result, there is a need for a wafer edge remediation system providing efficient and thorough remediation of aberrations and improving overall production yields.